The present invention generally relates to testing circuits implemented on programmable logic devices, and more particularly to providing input signals to a programmable logic device for testing operation of a circuit implemented thereon.
Field programmable gate arrays (FPGAs), first introduced by XILINX in 1985, are becoming increasingly popular devices for use in electronics systems. For example, communications systems frequently employ FPGAs for their re-programmability. In general, the use of FPGAs continues to grow at a rapid rate because FPGAs permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility through re-programmability. The capabilities of and specifications for XILINX FPGAs are set forth in xe2x80x9cThe Programmable Logic Data Book,xe2x80x9d published in 1998 by XILINX, Inc., the contents of which is incorporated herein by reference.
Where once a typical FPGA design comprised perhaps 5,000 gates, FPGA designs with 50,000 gates are now common, and FPGAs supporting 300,000 to 1,000,000 gates are available. New challenges for testing and debugging designs implemented on the devices have accompanied the growth in PLDs, particularly FPGAs. For example, large configuration bitstreams must be manipulated to test the PLDs. Thus, additional off-PLD storage and increased programming time are undesirable side effects of the growing size of configuration bitstreams.
In a test sequence that is presently used for designs implemented on PLDs, the configuration bitstream is downloaded to the device, selected input signals are provided to the device while advancing the device clock at selected times, and the state of the device is read back after having advanced the clock and provided the input signals. The state data can then be compared to expected state data to verify proper operation of the design.
In some PLDs, the data read back from the PLD correspond by position to the configuration bitstream downloaded to the PLD. In other PLDs, the configuration bitstream includes commands to replicate portions of the bitstream, so the data read back from the PLD includes more bits than the original bitstream. In either case, bits in the configuration bitstream that were used to program resources such as lookup tables, multiplexers, and signal line connections, and to initialize storage elements such as flip-flops, correspond to data read back from the PLD. The bitstream read back from a PLD includes two kinds of data: (1) the configuration data for determining the configuration of the PLD, which can be verified immediately after the configuration has been loaded into the PLD, and (2) state information stored in the storage elements in the PLD. The state of storage elements may change in running the test even though the states of bits used to program the programmable resources probably remain the same. Thus it may be desirable to repeatedly monitor states of some of the storage elements but not to monitor the configuration data.
To select the desired data from the data read back from the device, past practice included creating a mask indicating which bits of the data comprise the desired data. The size of the mask, therefore, was the same as the size of the configuration bitstream. Thus, prior systems had to process and provide storage for a large mask file, which could be larger than 1 MB, for example.
Communication between a host computer and an FPGA typically occurs through a cable that includes electronic devices. For example, the XChecker(trademark) cable available from Xilinx, Inc. includes an FPGA situated in the cable. Also in the XChecker cable is sufficient memory for configuring the destination PLD (not the FPGA in the cable) and verifying this configuration data, since in these modes the data are simply passed through from the host to the PLD or from the PLD to the host. However, the XChecker cable FPGA can also initiate and control readback of selected state data from the destination PLD, applying a readback clock signal to the destination PLD to control reading back of data into the XChecker cable memory, from where it can be read by the host computer.
The continued growth in number of programmable resources and storage elements in programmable logic devices will require additional time for reading back data from a programmable logic device for purposes of testing and debugging designs. Thus, testing designs may become more time-consuming using current techniques, thereby increasing product costs. Special hardware arrangements made to test and debug a circuit implemented on a PLD may also increase product costs. A method that address the aforementioned problems, as well as other related problems, is therefore desirable.
The invention provides a method and system for testing operation of a circuit implemented on a programmable logic device. In one embodiment, a circuit implemented in a programmable logic device is tested using a host processor coupled via an interface device to the programmable logic device. The interface device includes a plurality of signal pins connected to selected input pins of the programmable logic device for configuring the programmable logic device. Test vectors from the host processor are applied via the interface device to the selected input pins of the programmable logic device, and the states of one or more signals appearing on one or more output pins of the device are analyzed.
In another embodiment, a system is provided. The system comprises a host data processing system coupled to an interface device. During a configuration process the host configures the programmable logic device, and during a test process the host applies input test signals to selected pins of the programmable logic device. The host uses selected pins of the interface device twice, both for functions during configuration and to input test signals during the test process.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.